SESC Configure

SESC配置文件解析及测试

Posted by yuchen on April 16, 2016
SESC配置文件解析及测试

SESC配置文件及测试

1.SESC配置文件解析

  1. # 注释
  3. procsPerNode  = 4 # 4 核
  4. cacheLineSize = 64 # cache块大小
  5. issue         = 2 # 每个周期最多发射2条指令
  7. ##################################################################
  8. # cpucore  指定机器拥有四个相同的核，编号范围从0到3（上述procsPerNode定义为4），
  9. # 每个核的配置被描述在 [issueX]段.这些核可以通过板载mesh网络相互通信。
  10. ##################################################################
  11. cpucore[0:$(procsPerNode)-1] = 'issueX'
  14. ##############################
  15. # 处理器的配置  #
  16. ##############################
  17. [issueX]
  18. frequency       = 1e9 #1GHz
  20. ##################################################################
  21. # inorder设为false说明这是一个 out-of-order核，并且fetches, issues,  and
  22. # retires up to 2 instructions per cycle (参数“issue” 在前面已经设为2).
  23. ##################################################################
  24. inorder         = false
  25. fetchWidth      = $(issue)
  26. issueWidth      = $(issue)
  27. retireWidth     = $(issue)
  28. bb4Cycle        = 1 # 一个周期内可以取得基本块的数量，即一个周期内基本上可以获取多少个分支
  29. maxIRequests    = 4 # Max number of outstanding instruction requests
  30. interClusterLat = 2
  31. intraClusterLat = 1
  32. cluster[0]      = 'FXClusterIssueX'//配置整数运算指令
  33. cluster[1]      = 'FPClusterIssueX'//配置浮点数运算指令
  35. robSize         = 64    
  36. intRegs         = 64    
  37. fpRegs          = 64    
  38. bpred           = 'BPredIssueX'//配置分支预测器
  39. enableICache    = true
  40. dtlb            = 'FXDTLB'
  41. itlb            = 'FXITLB'
  42. dataSource      = "DMemory DL1"
  43. instrSource     = "IMemory IL1"
  44. OSType          = 'dummy' # Memory OS, either Dummy or std
  47. # 整数功能单元
  48. [FXClusterIssueX]
  49. winSize    = 12*$(Issue)+32 # number of entries in window
  50. recycleAt  = 'Execute'
  51. schedNumPorts = 4
  52. schedPortOccp = 1
  53. wakeUpNumPorts= 4
  54. wakeUpPortOccp= 1
  55. wakeupDelay   = 2
  56. schedDelay    = 1 # Minimum latency like a intraClusterLat
  57. iStoreLat  = 1
  58. iStoreUnit = 'LDSTIssueX'
  59. iLoadLat   = 1
  60. iLoadUnit  = 'LDSTIssueX'
  61. iALULat    = 1
  62. iALUUnit   = 'ALUIssueX'
  63. iBJLat     = 1
  64. iBJUnit    = 'ALUIssueX'
  65. iDivLat    = 12
  66. iDivUnit   = 'ALUIssueX'
  67. iMultLat   = 4
  68. iMultUnit  = 'ALUIssueX'
  70. [LDSTIssueX]
  71. Num = $(issue)/3+1
  72. Occ = 1
  74. [ALUIssueX]
  75. Num = $(issue)/3+1
  76. Occ = 1
  79. # 浮点数功能单元
  80. [FPClusterIssueX]
  81. winSize    = 8*$(issue)
  82. recycleAt  = 'Execute'
  83. schedNumPorts = 4
  84. schedPortOccp = 1
  85. wakeUpNumPorts= 4
  86. wakeUpPortOccp= 1
  87. wakeupDelay   = 2
  88. schedDelay    = 1 # Minimum latency like a intraClusterLat
  89. fpALULat   = 1
  90. fpALUUnit  = 'FPIssueX'
  91. fpMultLat  = 8
  92. fpMultUnit = 'FPIssueX'
  93. fpDivLat   = 20
  94. fpDivUnit  = 'FPIssueX'
  96. [FPIssueX]
  97. Num = $(issue)/2+1
  98. Occ = 1
  100. # 分支预测器配置
  101. [BPredIssueX]
  103. ##################################################################
  104. #"hybrid" 实际上是一个联合的预测器,  配有一个元预测器（有2048个entries），
  105. # 每一个entry是一个饱和计数器。
  106. ##################################################################
  107. type          = "oracle" # hybrid-->taken-->oracle
  108. BTACDelay     = 0 #Branch Taken ACcess Delay, 0表示执行时无障碍，非零表示一个分支常数延迟
  109. #下面的数据为不同的分支预测器所用
  110. l1size        = 1
  111. l2size        = 2*1024      
  112. l2Bits        = 1
  113. historySize   = 8   
  114. Metasize      = 2*1024  
  115. MetaBits      = 2
  116. localSize     = 2*1024
  117. localBits     = 2
  118. btbSize       = 256 
  119. btbBsize      = 1
  120. btbAssoc      = 2
  121. btbReplPolicy = 'LRU'
  122. btbHistory    = 0
  123. rasSize       = 32
  126. # memory translation mechanism
  127. [FXDTLB]
  128. size       = 64*8
  129. assoc      = 4
  130. bsize      = 8
  131. numPorts   = 2
  132. replPolicy = 'LRU'
  133. deviceType = 'cache' # libcore/GMemorySystem, options: dummy, cache, icache, smpcache
  135. [FXITLB]
  136. size       = 64*8
  137. assoc      = 4
  138. bsize      = 8
  139. numPorts   = 2
  140. replPolicy = 'LRU'
  141. deviceType = 'cache'
  143. ##############################
  144. # MEMORY SUBSYSTEM           #
  145. ##############################
  146. # instruction source--IL1
  147. [IMemory]
  148. deviceType    = 'icache'
  149. size          = 32*1024     
  150. assoc         = 4
  151. bsize         = $(cacheLineSize)
  152. writePolicy   = 'WB'
  153. replPolicy = 'LRU'
  154. protocol      = 'DMESI'
  155. numPorts      = 1
  156. portOccp      = 1
  157. hitDelay      = 1 
  158. missDelay     = 1                # this number is added to the hitDelay
  159. #displNotify   = false
  160. MSHR          = "iMSHR"
  161. lowerLevel    = "Router RTR sharedBy 1" # Format: [Type] [UserDefinedName] [ShareOption]
  162. sideLowerLevel = "" # Another lower level
  164. [iMSHR]
  165. type = 'single'
  166. size = 32
  167. bsize = $(cacheLineSize)
  169. # data source -- DL1
  170. [DMemory]
  171. deviceType    = 'smpcache' # SMP类型的cache
  173. size          = 16*1024 #  可以存储32KBytes 的数据
  174. assoc         = 4 # 4路组相联
  176. # 64­byte  block/line  size  (cacheLineSize在前面被定义为 64)
  177. bsize         = $(cacheLineSize)
  178. writePolicy   = 'WB' # a  write­back  cache (写策略)
  179. replPolicy = 'LRU' # 使用  LRU  置换策略
  180. protocol      = 'DMESI'
  181. numPorts      = 2 # 有两个端口，故一个周期可以处理2次访问
  182. portOccp      = 1 # Number of occupancy per port. 0: UnlimitedPort, 1:FullyPipelinedPort, other value: PortPipe
  183. hitDelay      = 1 #命中时间需要一个周期
  184. missDelay     = 1 # 未命中检测需要1个周期             
  186. # 如果出现一个miss，处理器会使用DMSHR (data miss handling registers)结构跟踪这个miss，
  187. # DMSHR被描述在[DMSHR]段，其拥有一个64-entry结构，且每个entry可以跟踪整个64字节块的一个miss。
  188. # 在一个miss上，L1 cache或从一个本地核L2cache的slice上请求数据或通过on­chip路由与其连接的其他核上
  189. # 的L2 slice上请求数据。
  190. MSHR          = "DMSHR"
  191. lowerLevel    = "Router RTR sharedBy 1"
  192. sideLowerLevel    = "L2Slice L2S" # Another lower level
  194. [DMSHR]
  195. type = 'single' # Options: none, nodeps, full, single, banked Check libsuc/MSHR
  196. size = 64
  197. bsize = $(cacheLineSize)
  200. [Router]
  201. deviceType = 'router'
  202. delay      = 1
  203. numPorts      = 2  # read / write
  204. portOccp      = 1
  205. dimX            = $(NOCdim) # This needs to be the same with NOC dimension
  206. dimY            = $(NOCdim) # This needs to be the same with NOC dimension
  207. lowerLevel    ="NOC NOC shared"
  209. [NOC]
  210. deviceType = 'booksim'
  211. booksim_config      = 'mesh22.booksim'
  212. booksim_output      = 'booksim.log'
  213. booksim_sample      = 1000000
  214. lowerLevel    = "MemoryCtrl MemCtrl shared"
  216. [L2Slice]  # L2 Cache
  217. deviceType    = 'slicecache'
  218. inclusive     = false
  219. size          = 1*1024*1024 # 一个slice大小为 1  MB  (所以在此， L2  cache 总大小是4MB),
  220. assoc         = 16 # 16路组相联
  221. bsize         = $(cacheLineSize) # 64字节块大小
  222. writePolicy   = 'WB' #  回写策略
  223. replPolicy = 'LRU' #  LRU置换策略
  224. numPorts      = 2                #  2  ports,one for L1, one for snooping
  225. portOccp      = 1       # 一个cache的吞吐量
  226. hitDelay      = 12 # 命中时间需要12­cycle
  227. missDelay     = 12               # 检测一个miss需要12  cycles
  228. numPortsDir      = 1             
  229. portOccpDir      = 1
  230. hitDelayDir      = 1
  232. MSHR          = 'L2MSHR' # 使用一个 64­entry MSHR 去跟踪misses
  233. # 当出现一个miss时，该miss将被本地on­chip路由器处理，本地on­chip路由器使用板载网络 (NOC)
  234. # 传递消息给内存控制器。接着，内存控制器使用 off­chip 处理器内存总线访问主存。主存被配置在
  235. # [Memory]段，其被模型化一个拥有200 cycle延迟的极大的cache。
  237. lowerLevel    = "Router RTR sharedBy 1"
  239. [L2MSHR]
  240. size =  64
  241. type = 'single'
  242. bsize = $(cacheLineSize)
  244. [MemoryCtrl]
  245. deviceType    = 'memoryController'
  246. numPorts      = 8   # 8 channel
  247. portOccp      = 1
  248. delay         = 1
  249. lowerLevel    = "MemoryBus MemoryBus"
  251. [MemoryBus]
  252. deviceType    = 'bus'
  253. numPorts      = 8
  254. portOccp      = $(cacheLineSize) / 8   # assuming 8*8 Gbyte/s  
  255. delay         = 5
  256. lowerLevel    = "Memory Memory"
  258. [Memory]
  259. deviceType    = 'niceCache'
  260. size          = 64
  261. assoc         = 1
  262. bsize         = 64
  263. writePolicy   = 'WB'
  264. replPolicy = 'LRU'
  265. numPorts      = 1
  266. portOccp      = 1
  267. hitDelay      = 200 
  268. missDelay     = 10000
  269. MSHR          = NoMSHR
  270. lowerLevel    = 'voidDevice'
  272. [NoMSHR]
  273. type = 'none'
  274. size = 128
  275. bsize = 64
  277. [voidDevice]
  278. deviceType    = 'void'
  280. ############################
  281. #     BEGIN MIPSEMUL       #
  282. ############################
  284. [FileSys]
  285. mount="/bin=/mipsroot/tools/bin:/lib=/mipsroot/tools/lib:/tools=/mipsroot/tools"

2.分支预测器的类型测试(hybrid–>taken–>oracle)

  2. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -olu.out -elr.err lu.mipseb -n32 -p 1 
  3. # File  : sesc_lu.mipseb.b4QrwJ :       Sat Apr 16 03:33:27 2016
  4.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  5.     389.963 KIPS      0.5564 MHz       0.830 secs       0.462 msec
  6. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  7.    0   55.215  hybrid       91.05% ( 99.89% of  11.34%)  89.92% ( 95.81% of  57.74%)   0.00% 
  8.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  9.    0      323669   9.49%  18.01%   9.25%  55.68%   7.57%  :     12.66%     302 inst/repl  :  ALUIssueX 2.80 
  10. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  11.    0  0.70       461822  35.0   0.0   0.0   0.1  18.0   0.0   0.0   0.0   0.0   45.2    0.1    1.6 
  12. ################################################################################
  13. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  14.    0  DL1 0.0   0.42% ( 0.1%, 0.3%) 92.46%  0.05GB/s :  MemoryBus 0 MB/s : 
  15. ################################################################################
  16. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  17.    0  IL1 0.0   0.45% ( 0.5%, 0.0%) 192.05%  0.11GB/s :  MemoryBus 0 MB/s : 
  19. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -olu.out -elr.err lu.mipseb -n32 -p 1 
  20. # File  : sesc_lu.mipseb.ZOV04r :       Sat Apr 16 03:40:03 2016
  21.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  22.     363.673 KIPS      0.5692 MHz       0.890 secs       0.507 msec
  23. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  24.    0   26.849  taken        67.56% ( 99.89% of  11.34%)  63.42% ( 94.16% of  59.71%)   0.00% 
  25.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  26.    0      323669   9.49%  18.01%   9.25%  55.68%   7.57%  :      5.48%     306 inst/repl  :  ALUIssueX 2.18 
  27. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  28.    0  0.64       506617  31.9   0.0   0.0   0.1   4.1   0.0   0.0   0.0   0.0   62.8    0.0    1.1 
  29. ################################################################################
  30. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  31.    0  DL1 0.0   0.39% ( 0.1%, 0.3%) 98.40%  0.04GB/s :  MemoryBus 0 MB/s : 
  32. ################################################################################
  33. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  34.    0  IL1 0.0   0.45% ( 0.4%, 0.0%) 193.55%  0.10GB/s :  MemoryBus 0 MB/s : 
  36. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -olu.out -elr.err lu.mipseb -n32 -p 1 
  37. # File  : sesc_lu.mipseb.9o5lQb :       Sat Apr 16 03:42:42 2016
  38.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  39.     404.586 KIPS      0.5474 MHz       0.800 secs       0.438 msec
  40. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  41.    0   98.266  oracle       96.50% ( 99.89% of  11.34%)  96.07% ( 94.16% of  59.71%)   0.00% 
  42.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  43.    0      323669   9.49%  18.01%   9.25%  55.68%   7.57%  :     12.80%     300 inst/repl  :  ALUIssueX 3.15 
  44. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  45.    0  0.74       437914  37.0   0.0   0.0   0.1  21.2   0.0   0.0   0.0   0.0   39.6    0.1    2.1 
  46. ################################################################################
  47. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  48.    0  DL1 0.0   0.42% ( 0.1%, 0.3%) 92.41%  0.05GB/s :  MemoryBus 0 MB/s : 
  49. ################################################################################
  50. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  51.    0  IL1 0.0   0.45% ( 0.5%, 0.0%) 192.02%  0.11GB/s :  MemoryBus 0 MB/s :

3.指令发射宽度测试(issue：2–>4)

  1. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -olu.out -elr.err lu.mipseb -n32 -p 1 
  2. # File  : sesc_lu.mipseb.W213wq :       Sat Apr 16 04:01:07 2016
  3.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  4.     449.540 KIPS      0.5527 MHz       0.720 secs       0.398 msec
  5. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  6.    0   67.584  hybrid       91.05% ( 99.89% of  11.34%)  89.92% ( 95.81% of  57.74%)   0.00% 
  7.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  8.    0      323669   9.49%  18.01%   9.25%  55.68%   7.57%  :     12.68%     302 inst/repl  :  ALUIssueX 0.25 
  9. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  10.    0  0.81       397915  20.3   0.0   0.0   0.0  29.1   0.0   0.0   0.0   0.0   48.9    0.1    1.6 
  11. ################################################################################
  12. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  13.    0  DL1 0.0   0.42% ( 0.1%, 0.3%) 92.59%  0.05GB/s :  MemoryBus 0 MB/s : 
  14. ################################################################################
  15. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  16.    0  IL1 0.0   0.85% ( 0.9%, 0.0%) 100.64%  0.12GB/s :  MemoryBus 0 MB/s : 
  17. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -olu.out -elr.err lu.mipseb -n32 -p 1 
  18. # File  : sesc_lu.mipseb.hwtxXj :       Sat Apr 16 04:01:27 2016
  19.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  20.     431.559 KIPS      0.5780 MHz       0.750 secs       0.433 msec
  21. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  22.    0   30.247  taken        67.56% ( 99.89% of  11.34%)  63.42% ( 94.16% of  59.71%)   0.00% 
  23.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  24.    0      323669   9.49%  18.01%   9.25%  55.68%   7.57%  :      5.50%     305 inst/repl  :  ALUIssueX 0.22 
  25. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  26.    0  0.75       433486  18.7   0.0   0.0   0.0  11.4   0.0   0.0   0.0   0.0   68.6    0.0    1.3 
  27. ################################################################################
  28. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  29.    0  DL1 0.0   0.40% ( 0.1%, 0.3%) 97.37%  0.05GB/s :  MemoryBus 0 MB/s : 
  30. ################################################################################
  31. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  32.    0  IL1 0.0   0.83% ( 0.8%, 0.0%) 102.55%  0.11GB/s :  MemoryBus 0 MB/s : 
  33. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -olu.out -elr.err lu.mipseb -n32 -p 1 
  34. # File  : sesc_lu.mipseb.Y8YKpM :       Sat Apr 16 04:01:40 2016
  35.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  36.     469.086 KIPS      0.5336 MHz       0.690 secs       0.368 msec
  37. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  38.    0   126.080  oracle       96.50% ( 99.89% of  11.34%)  96.07% ( 94.16% of  59.71%)   0.00% 
  39.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  40.    0      323669   9.49%  18.01%   9.25%  55.68%   7.57%  :     12.93%     301 inst/repl  :  ALUIssueX 0.25 
  41. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  42.    0  0.88       368151  22.0   0.0   0.0   0.0  33.4   0.0   0.0   0.0   0.0   42.6    0.1    1.9 
  43. ################################################################################
  44. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  45.    0  DL1 0.0   0.42% ( 0.1%, 0.3%) 92.49%  0.06GB/s :  MemoryBus 0 MB/s : 
  46. ################################################################################
  47. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  48.    0  IL1 0.0   0.85% ( 0.9%, 0.0%) 100.45%  0.13GB/s :  MemoryBus 0 MB/s :

4. Cache测试(size:32KB–>16KB,numPorts:2–>4)

  1. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -oocean.out -eocean.err ocean.mipseb -n 258 -p 1 
  2. # File  : sesc_ocean.mipseb.KYbtOE :       Sat Apr 16 05:31:48 2016
  3.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  4.     250.623 KIPS      0.4201 MHz    1956.200 secs     821.856 msec
  5. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  6.    0   98.401  oracle       99.94% ( 99.99% of   0.32%)  99.94% ( 99.93% of  88.33%)   0.00% 
  7.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  8.    0   490268438   4.61%  22.88%   6.18%  31.74%  34.59%  :      0.80%   582959 inst/repl  :  LDSTIssueX 0.23 
  9. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  10.    0  0.60    821855801  14.9   0.0   0.0   0.3  84.5   0.0   0.0   0.0   0.0    0.0    0.2    0.0 
  11. ################################################################################
  12. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  13.    0  DL1 0.2   5.76% ( 4.7%, 1.1%) 124.25%  0.79GB/s :  MemoryBus 0 MB/s : 
  14. ################################################################################
  15. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  16.    0  IL1 0.0   0.00% ( 0.0%, 0.0%) 92.02%  0.00GB/s :  MemoryBus 0 MB/s : 
  17. # Bench : sesc.opt -c /home/ud233user/sesc/confs/cmp4-noc.conf -oocean.out -eocean.err ocean.mipseb -n 258 -p 1 
  18. # File  : sesc_ocean.mipseb.KAxWgJ :       Sat Apr 16 07:19:24 2016
  19.       Exe Speed        Exe MHz         Exe Time         Sim Time (1000MHz)
  20.     228.784 KIPS      0.4045 MHz    2142.930 secs     866.814 msec
  21. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  22.    0   98.629  oracle       99.94% ( 99.99% of   0.32%)  99.94% ( 99.93% of  88.33%)   0.00% 
  23.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  24.    0   490268438   4.61%  22.88%   6.18%  31.74%  34.59%  :      0.80%   576786 inst/repl  :  LDSTIssueX 0.23 
  25. Proc  IPC        Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  26.    0  0.57    866813880  14.1   0.0   0.0   0.3  85.4   0.0   0.0   0.0   0.0    0.0    0.2    0.0 
  27. ################################################################################
  28. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  29.    0  DL1 0.0   7.03% ( 5.8%, 1.2%) 125.16%  0.93GB/s :  MemoryBus 0 MB/s : 
  30. ################################################################################
  31. Proc  Cache Occ MissRate (RD, WR) %DMemAcc MB/s : ... 
  32.    0  IL1 0.0   0.00% ( 0.0%, 0.0%) 92.02%  0.00GB/s :  MemoryBus 0 MB/s :

5.利用异构多核运行程序

SESC本来大多用来研究SMP、CMP问题，很少用来研究AMP问题。但是徐友军师兄，对其配置文件及源码进行了一些更改，使得其可以用于研究AMP问题。
我们运行模拟器时需要使用配置文件（如前解析），使用功耗功能时需要执行
make sesc.conf和make power.conf命令：

  • make sesc.conf命令将源码中的模板配置文件sesc.conf和shared.conf复制到当前文件夹（sesc.conf会将shared.conf包含进来）;
  • make power.conf命令将生成wattchify和 cactify文件。
    • wattchify利用sesc.conf生成tmp.conf；
    • cactify 利用tmp.conf生成power.conf。
    • 最后删除tmp.conf。

正如前面所述，’issueX’段对核进行了配置，我们只需要先成一种核的power.conf文件（文件1），然后在另外一个文件夹中将issueX更改为其他标志（如issueY），然后修改里面相应段的配置，利用修改后的文件再生成另外一种核的power.conf文件（文件2），合并文件1和文件2，修改相同下标处（使得下标连贯）即可生成AMP的配置文件。

  • 这里使用的配置文件如下(8核，四大核四小核)
  1. #BEGIN Configuration used. Extracted from "S.conf":
  2. procsPerNode=1
  3. thermal   ='SescTherm'
  4. gNetwork  ='m3tnetwork'
  5. L2ll      ="AdvMem MemBus shared"
  6. depth_S   =2
  7. pageSize  =4096
  8. memSizing_S=1
  9. STUnits   =1
  10. technology='techParam'
  11. wattchDataCacheEnergy=1.065153e+00
  12. cpucore[0:4]='issueX_S'
  13. cpucore[5:8]='issueX_L'
  14. LDUnits   =1
  15. nCPUs     =9
  16. NoMigration=false
  17. UseTLS    =0
  18. traceMode ='qemusparc'
  19. AdvMemMap ='M3TMemMap'
  20. thermSpot ='SescSpot'
  21. issue_S   =2
  22. floorplan ='layoutDescr'
  23. [LDIssueX_S]
  24. Num       =1
  25. Occ       =1
  26. [techParam]
  27. numberOfFanouts=1
  28. padCapacitance=1
  29. tech      =70
  30. microstripLength=10
  31. clockTreeStyle='htree'
  32. skewBudget=20
  33. optimalNumberOfBuffer=3
  34. loadInClockNode=20
  35. randomLogicStyle=1
  36. loadCapacitance=1
  37. areaOfChip=200
  38. numberOfClusters=1
  39. numberOfioBufferStage=5
  40. numberOfFunctions=4
  41. numberofGates=30000
  42. numberOfFanins=4
  43. frequency =2.400000e+09
  44. [DataL1_S]
  45. portOccp  =1
  46. blockName ='Dcache'
  47. missDelay =1
  48. RdHitEnergy=1.065153e+00
  49. WrHitEnergy=1.065153e+00
  50. size      =32768
  51. assoc     =4
  52. WrMissEnergy=2.130306e+00
  53. writePolicy='WB'
  54. hitDelay  =2
  55. bsize     =64
  56. lowerLevel="CommonBus Bus shared"
  57. MSHR      ='DL1MSHR_S'
  58. replPolicy='RANDOM'
  59. skew      =false
  60. numPorts  =1
  61. RdMissEnergy=2.130306e+00
  62. deviceType='cache'
  63. [issueX_S]
  64. windowCheckEnergy=4.349804e-02
  65. instQueueSize=12
  66. maxStores =38
  67. btbEnergy =2.156033e-01
  68. intRegs   =64
  69. iALUEnergy=3.417957e-01
  70. LSQBanks  =1
  71. ldqCheckEnergy=1.044431e-01
  72. renameEnergy=1.732633e-01
  73. clockEnergy=3.142553e+00
  74. windowRdWrEnergy=2.224685e-01
  75. windowSelEnergy=5.741436e-03
  76. inorder   =true
  77. resultBusEnergy=4.949979e-02
  78. wrRegEnergy=1.833822e-01
  79. dataSource="DataL1_S DL1_S"
  80. areaFactor=2.562500e-01
  81. bb4Cycle  =1
  82. robSize   =100
  83. maxBranches=16
  84. totEnergy =1.306076e+01
  85. interClusterLat=2
  86. cluster   ='FXClusterIssueX_S'
  87. cluster[1:1]='FPClusterIssueX_S'
  88. bpredEnergy=8.987931e-02
  89. forwardBusEnergy=4.949979e-02
  90. dtlb      ='FXDTLB_S'
  91. issueWrongPath=true
  92. archBits  =32
  93. decodeDelay=3
  94. rasEnergy =0.000000e+00
  95. fpRegs    =64
  96. minTLBMissDelay=16
  97. itlb      ='FXITLB_S'
  98. stqRdWrEnergy=1.462314e+00
  99. fpALUEnergy=1.047439e+00
  100. instrSource="InstL1_S IL1_S"
  101. bpred     ='BPredIssueX_S'
  102. fetchWidth=6
  103. maxLoads  =42
  104. issueWidth=2
  105. rdRegEnergy=1.833822e-01
  106. robEnergy =6.256428e-02
  107. stqCheckEnergy=9.549810e-02
  108. retireWidth=2
  109. renameDelay=3
  110. stForwardDelay=1
  111. regFileDelay=3
  112. OSType    ='std'
  113. maxIRequests=3
  114. ldqRdWrEnergy=1.429250e+00
  115. enableICache=true
  116. bpredDelay=1
  117. [L2Cache]
  118. bsize     =64
  119. writePolicy='WB'
  120. blockName ='L2'
  121. hitDelay  =10
  122. RdMissEnergy=7.798407e+00
  123. missDelay =4
  124. WrHitEnergy=3.899203e+00
  125. numPorts  =1
  126. portOccp  =1
  127. size      =524288
  128. replPolicy='LRU'
  129. assoc     =8
  130. WrMissEnergy=7.798407e+00
  131. RdHitEnergy=3.899203e+00
  132. MSHR      ='MSHRL2_S'
  133. lowerLevel="AdvMem MemBus shared"
  134. deviceType='cache'
  135. [BestBPred]
  136. BTACDelay =0
  137. btbReplPolicy='LRU'
  138. btbAssoc  =2
  139. tbits     =5
  140. rasSize   =0
  141. btbSize   =2048
  142. type      ='ogehl'
  143. tcbits    =7
  144. tsize     =2048
  145. mtables   =6
  146. btbBsize  =1
  150. [PBuff]
  151. hitDelay  =3
  152. missDelay =2
  153. buffCache ='PBuffBuff_S'
  154. learnHitDelay=4
  155. streamCache='PBuffStream_S'
  156. maxStride =512
  157. deviceType='prefbuff'
  158. depth     =1
  159. learnMissDelay=6
  160. lowerLevel="AdvMem MemBus shared"
  161. missWindow=16
  162. [SimParams]
  163. hotspotLogFile='scooreX.out'
  164. setBinaryLog=1
  165. sampleRate=10
  166. dtmUsed   =0
  167. floorPlanFile='scooreX.flp'
  168. omitLateralR=0
  169. [TaskScalar]
  170. SyncOnRestart=3
  171. VersionSize=32
  172. bsize     =64
  173. MFThreshold=4
  174. IDP       ='IntPred1_S'
  175. MLThreshold=32
  176. [InstL1_S]
  177. hitDelay  =2
  178. WrHitEnergy=1.135176e+00
  179. size      =32768
  180. portOccp  =1
  181. deviceType='icache'
  182. WrMissEnergy=2.270351e+00
  183. numPorts  =2
  184. MSHR      ='InstL1MSHR_S'
  185. RdHitEnergy=1.135176e+00
  186. lowerLevel="L2Cache L2 shared"
  187. assoc     =2
  188. writePolicy='WB'
  189. RdMissEnergy=2.270351e+00
  190. replPolicy='LRU'
  191. bsize     =64
  192. blockName ='Icache'
  193. missDelay =0
  194. [STIssueX_S]
  195. Occ       =1
  196. Num       =1
  197. [IntPred1_S]
  198. RdMissEnergy=1.303039e+00
  199. WrMissEnergy=1.303039e+00
  200. RdHitEnergy=6.515196e-01
  201. ReplPolicy='LRU'
  202. Assoc     =32
  203. deviceType='cache'
  204. IDPnChildMax=4
  205. WrHitEnergy=6.515196e-01
  206. portOccp  =1
  207. bSize     =8
  208. size      =256
  209. numPorts  =1
  210. [BPredIssueX_S]
  211. btbAssoc  =2
  212. btbBsize  =1
  213. historySize=11
  214. btbReplPolicy='LRU'
  215. localSize =16384
  216. Metasize  =16384
  217. BTACDelay =0
  218. localBits =2
  219. l2Bits    =1
  220. btbSize   =2048
  221. type      ='hybrid'
  222. MetaBits  =2
  223. rasSize   =0
  224. bpred4Cycle=1
  225. l2size    =16384
  226. l1size    =1
  227. [FXDTLB_S]
  228. deviceType='tlb'
  229. numPorts  =1
  230. replPolicy='LRU'
  231. RdMissEnergy=2.762933e+00
  232. WrHitEnergy=1.381467e+00
  233. RdHitEnergy=1.381467e+00
  234. bsize     =8
  235. assoc     =64
  236. size      =512
  237. WrMissEnergy=2.762933e+00
  238. [PBuffStream_S]
  239. portOccp  =3
  240. RdHitEnergy=1.052776e+00
  241. WrHitEnergy=1.052776e+00
  242. ReplPolicy='LRU'
  243. WrMissEnergy=2.105553e+00
  244. RdMissEnergy=2.105553e+00
  245. Assoc     =16
  246. numPorts  =2
  247. Size      =128
  248. BSize     =8
  249. deviceType='cache'
  250. [SescSpot]
  251. InterfaceMaterialThickness=7.500000e-05
  252. SpreaderThickness=1.000000e-03
  253. ConvectionCapacitance=1.404000e+02
  254. SpreaderLength=3.000000e-02
  255. DTMUsed   =false
  256. ChipThickness=5.000000e-04
  257. HeatsinkThinkness=6.900000e-03
  258. ConvectionResistance=1.000000e-01
  259. HeatsinkLength=6.000000e-02
  260. DTMTempThreshhold=1.118000e+02
  261. [AdvMem]
  262. numPorts  =1
  263. busWidth  =64
  264. delay     =1
  265. deviceType='bus'
  266. lowerLevel='BigMem_S'
  267. iopins    =true
  268. portOccp  =32
  269. [BigMem_S]
  270. WrMissEnergy=0.000000e+00
  271. hitDelay  =490
  272. MSHR      ='BigMemMSHR_S'
  273. numPorts  =1
  274. size      =1024
  275. assoc     =1
  276. deviceType='niceCache'
  277. bsize     =64
  278. writePolicy='WB'
  279. RdMissEnergy=0.000000e+00
  280. WrHitEnergy=0.000000e+00
  281. RdHitEnergy=0.000000e+00
  282. lowerLevel='voidDevice'
  283. replPolicy='LRU'
  284. missDelay =1600000
  285. portOccp  =1
  286. [layer1]
  287. thickness =1.000000e-03
  288. material  ='Silicon'
  289. [AmbientTemperature]
  290. initialTemp=60
  291. offsetConstant=2.731500e+02
  292. ambientTemp=40
  293. [Virtual]
  294. specHeat  =0
  295. conductance=0
  296. density   =0
  297. alpha     =0
  298. [FXClusterIssueX_S]
  299. iDivUnit  ='ALUIssueX_S'
  300. schedNumPorts=4
  301. schedPortOccp=1
  302. recycleAt ='Execute'
  303. iLoadUnit ='LDIssueX_S'
  304. iMultUnit ='ALUIssueX_S'
  305. winSize   =56
  306. iDivLat   =207
  307. iMultLat  =10
  308. iStoreUnit='STIssueX_S'
  309. schedDelay=1
  310. iLoadLat  =1
  311. blockName ='IntWin'
  312. windowRdWrEnergy=5.560074e-01
  313. iALULat   =1
  314. wakeUpNumPorts=4
  315. iBJUnit   ='ALUIssueX_S'
  316. iALUUnit  ='ALUIssueX_S'
  317. iBJLat    =1
  318. wakeupDelay=3
  319. wakeUpPortOccp=1
  320. iStoreLat =1
  321. [FXITLB_S]
  322. size      =256
  323. RdHitEnergy=6.696175e-01
  324. RdMissEnergy=1.339235e+00
  325. assoc     =32
  326. deviceType='tlb'
  327. bsize     =8
  328. WrHitEnergy=6.696175e-01
  329. numPorts  =1
  330. replPolicy='LRU'
  331. WrMissEnergy=1.339235e+00
  333. [CommonBus]
  334. busWidth  =32
  335. buffWCReqs=1
  336. deviceType='bus'
  337. lowerLevel="L2Cache L2 shared"
  338. delay     =3
  339. portOccp  =1
  340. numPorts  =2
  341. busLength =7500
  342. [layer5]
  343. heat_sink_width=1.000000e-01
  344. heat_sink_resistance=1.300000e-01
  345. heat_sink_fins=5
  346. thickness =1.000000e-01
  347. heat_sink_height=1.000000e-01
  348. heat_sink =true
  349. material  ='Copper'
  350. [ucoolConf]
  351. current   =4.000000e-01
  352. seebeck   =2.400000e-04
  353. coupledDevices=12
  354. Resistivity=2.857000e-06
  355. Height    =1.000000e-04
  356. crossSection=5.000000e-02
  357. Width     =1.000000e-04
  358. conductivity=3.000000e+00
  359. [PBuffBuff_S]
  360. ReplPolicy='LRU'
  361. RdMissEnergy=3.573363e+00
  362. deviceType='cache'
  363. numPorts  =2
  364. Size      =16384
  365. RdHitEnergy=1.786681e+00
  366. Assoc     =4
  367. WrMissEnergy=3.573363e+00
  368. BSize     =32
  369. WrHitEnergy=1.786681e+00
  370. portOccp  =3
  371. [FPClusterIssueX_S]
  372. schedPortOccp=1
  373. blockName ='FPWin'
  374. schedNumPorts=4
  375. schedDelay=1
  376. fpDivUnit ='FP0IssueX_S'
  377. wakeUpPortOccp=1
  378. recycleAt ='Execute'
  379. fpMultUnit='FP0IssueX_S'
  380. fpDivLat  =60
  381. windowRdWrEnergy=4.776964e-01
  382. fpMultLat =4
  383. wakeupDelay=3
  384. winSize   =24
  385. fpALUUnit ='FP0IssueX_S'
  386. fpALULat  =5
  387. wakeUpNumPorts=4
  388. [SescTherm]
  389. CyclesPerSample=20000
  390. TimeIncrement=2.500000e-01
  391. ucool     ='ucoolConf'
  392. MeshResolutionSpreader=1.000000e-01
  393. MeshResolutionChip=3.000000e-03
  394. initialTemp=2.500000e+01
  395. MeshResolutionSink=5.000000e-01
  396. FanVelocity=2.000000e+00
  397. material[2:2]='Virtual'
  398. material[1:1]='Copper'
  399. material  ='Silicon'
  400. ambientTemp=40
  401. layer[5:5]='layer5'
  402. layer[4:4]='layer4'
  403. layer[3:3]='layer3'
  404. layer[2:2]='layer2'
  405. layer[1:1]='layer1'
  406. [HeatSink]
  407. convecR   =1.000000e-01
  408. convecC   =1.404000e+02
  409. heatsinkThick=6.900000e-02
  410. heatsinkSide=6.000000e-02
  411. [MSHRL2_S]
  412. type      ='full'
  413. bsize     =64
  414. size      =32
  415. [layer3]
  416. thickness =2.000000e-03
  417. material  ='Copper'
  418. [HeatSpreader]
  419. spreaderThick=1.000000e-03
  420. spreaderSide=3.000000e-02
  422. [Copper]
  423. alpha     =1.170000e-04
  424. density   =8933
  425. conductance=401
  426. specHeat  =385
  427. [BPredTaken]
  428. btbSize   =1
  429. btbBsize  =1
  430. rasSize   =1
  431. btbReplPolicy='LRU'
  432. btbAssoc  =1
  433. type      ='Static'
  434. [Silicon]
  435. alpha     =8.920000e-05
  436. density   =2330
  437. specHeat  =712
  438. conductance=148
  439. [FileSys]
  440. mount     =''
  441. [ALUIssueX_S]
  442. Occ       =1
  443. Num       =2
  444. [BigMemMSHR_S]
  445. bsize     =64
  446. size      =32
  447. type      ='none'
  448. [InterfaceMaterial]
  449. interfaceThick=7.500000e-05
  450. [FP0IssueX_S]
  451. Occ       =1
  452. Num       =1
  453. [InstL1MSHR_S]
  454. type      ='full'
  455. size      =4
  456. bsize     =64
  457. [miscEnergy]
  458. combWriteEnergy=3.952196e-02
  459. [DL1MSHR_S]
  460. type      ='full'
  461. size      =32
  462. bsize     =64
  463. [ChipSpecs]
  464. tempThreshold=1.118000e+02
  465. chipThickness=5.000000e-04
  466. [voidDevice]
  467. deviceType='void'
  468. #END Configuration used. Extracted from "S.conf":
  469. #BEGIN Configuration used. Extracted from "L.conf":
  470. procsPerNode=1
  471. thermal   ='SescTherm'
  472. gNetwork  ='m3tnetwork'
  473. L2ll      ="AdvMem MemBus shared"
  474. pageSize  =4096
  475. STUnits   =3
  476. memSizing_L=1
  477. wattchDataCacheEnergy=1.065153e+00
  480. LDUnits   =3
  481. nCPUs     =4
  482. NoMigration=false
  483. UseTLS    =0
  484. traceMode ='qemusparc'
  485. AdvMemMap ='M3TMemMap'
  486. issue_L   =3
  487. depth_L   =3
  488. thermSpot ='SescSpot'
  489. floorplan ='layoutDescr'
  492. [FXDTLB_L]
  493. WrHitEnergy=1.246505e+00
  494. bsize     =8
  495. assoc     =64
  496. replPolicy='LRU'
  497. WrMissEnergy=2.493009e+00
  498. deviceType='tlb'
  499. numPorts  =1
  500. RdHitEnergy=1.246505e+00
  501. RdMissEnergy=2.493009e+00
  502. size      =512
  503. [layoutDescr]
  504. blockDescr="FPWin           0.0025         0.001          0.000          0.000"
  505. blockDescr[1:1]="FPReg           0.0025         0.001          0.0025         0.000"
  506. blockDescr[3:3]="IntWin          0.003          0.0015         0.0035         0.001"
  507. blockDescr[4:4]="IntReg          0.002          0.0015         0.0065         0.001"
  508. blockDescr[6:6]="FPRAT          0.0035         0.0005         0.000          0.0010"
  509. blockDescr[7:7]="IntRAT          0.0035         0.0010         0.000          0.0015"
  510. blockDescr[10:10]="ROB             0.0025         0.0015         0.0035         0.0025"
  511. blockDescr[11:11]="Icache          0.0045        0.0015         0.000          0.004"
  512. blockDescr[12:12]="Dcache          0.005         0.0015         0.005          0.004"
  513. blockDescr[13:13]="MSHR            0.0005        0.0015         0.0045         0.004"
  514. blockDescr[14:14]="L2              0.0100        0.0055         0.000          0.0055"
  515. blockDescr[2:2]="FPUnitMult          0.0015          0.001         0.0085         0.000"
  516. blockDescr[18:18]="FPUnitAlu          0.0020          0.001         0.0065          0.000"
  517. blockDescr[19:19]="FPUnitDiv          0.0015          0.001         0.005         0.000"
  518. blockDescr[5:5]="IntUnitMult         0.0015         0.0005         0.0085         0.0020"
  519. blockDescr[20:20]="IntUnitAlu         0.0015         0.0005         0.0085         0.0015"
  520. blockDescr[21:21]="IntUnitDiv         0.0015         0.0005         0.0085         0.001"
  521. blockDescr[9:9]="LDQ             0.002          0.0015         0.006          0.0025"
  522. blockDescr[17:17]="STQ            0.002          0.0015         0.008          0.0025"
  523. blockDescr[8:8]="RAS           0.0005         0.00075         0.003          0.00325"
  524. blockDescr[16:16]="Bpred         0.0030         0.00075         0.000          0.00325"
  525. blockDescr[15:15]="BTB          0.0035         0.00075         0.000          0.0025"
  526. blockMatch='Proc(0)_FPClusterIssueX'
  527. blockMatch[1:1]="Proc(0):rdFPRegEnergy  Proc(0):wrFPRegEnergy"
  528. blockMatch[3:3]='Proc(0)_FXClusterIssueX*'
  529. blockMatch[4:4]="Proc(0):rdIRegEnergy   Proc(0):wrIRegEnergy"
  530. blockMatch[6:6]='Proc(0):renameEnergy'
  531. blockMatch[7:7]='Proc(0):renameEnergy'
  532. blockMatch[10:10]='Proc(0):robEnergy'
  533. blockMatch[11:11]="P(0)_IL1* P(0)_ITLB*"
  534. blockMatch[12:12]='P(0)_DTLB*'
  535. blockMatch[13:13]="P(0)_DL1_MSHR P(0)_PBuff"
  536. blockMatch[14:14]="L2 niceCache"
  537. blockMatch[2:2]='Cluster(0):fpMult'
  538. blockMatch[18:18]='Cluster(0):fpALU'
  539. blockMatch[19:19]='Cluster(0):fpDiv'
  540. blockMatch[5:5]='Cluster(0):iMult'
  541. blockMatch[20:20]='Cluster(0):iALU'
  542. blockMatch[21:21]='Cluster(0):iDiv'
  543. blockMatch[9:9]="FULoad(0) FUMemory(0)"
  544. blockMatch[17:17]="FUStore(0) FUMemory(0)"
  545. blockMatch[8:8]='BPred(0)_RAS'
  546. blockMatch[16:16]='BPred(0)_hybrid'
  547. blockMatch[15:15]='BPred(0)_BTB'
  548. [layer4]
  549. heat_spreader_height=2.000000e-02
  550. material  ='Copper'
  551. thickness =2.000000e-02
  552. heat_spreader_width=2.000000e-02
  553. heat_spreader=true
  556. [issueX_L]
  557. retireWidth=3
  558. renameDelay=3
  559. OSType    ='std'
  560. dataSource="DataL1_L DL1_L"
  561. resultBusEnergy=1.528119e-01
  562. windowSelEnergy=1.107277e-02
  563. bpredDelay=1
  564. issueWrongPath=true
  565. renameEnergy=2.000427e-01
  566. minTLBMissDelay=16
  567. interClusterLat=2
  568. stForwardDelay=1
  569. fpRegs    =80
  570. forwardBusEnergy=1.528119e-01
  571. bb4Cycle  =1
  572. robEnergy =7.539995e-01
  573. wrRegEnergy=3.438024e-01
  574. maxIRequests=3
  575. areaFactor=5.687500e-01
  576. robSize   =128
  577. maxLoads  =48
  578. decodeDelay=3
  579. itlb      ='FXITLB_L'
  580. inorder   =false
  581. intRegs   =96
  582. instrSource="InstL1_L IL1_L"
  583. regFileDelay=3
  584. stqCheckEnergy=1.044431e-01
  585. cluster   ='FXClusterIssueX_L'
  586. cluster[1:1]='FPClusterIssueX_L'
  587. dtlb      ='FXDTLB_L'
  588. windowCheckEnergy=8.454319e-02
  589. ldqCheckEnergy=1.178606e-01
  590. enableICache=true
  591. bpred     ='BPredIssueX_L'
  592. rasEnergy =0.000000e+00
  593. stqRdWrEnergy=1.507999e+00
  594. ldqRdWrEnergy=1.474934e+00
  595. totEnergy =1.464537e+01
  596. instQueueSize=12
  597. rdRegEnergy=3.438024e-01
  598. fpALUEnergy=1.047439e+00
  599. maxStores =42
  600. bpredEnergy=8.987931e-02
  601. btbEnergy =2.156033e-01
  602. issueWidth=3
  603. iALUEnergy=3.417957e-01
  604. fetchWidth=6
  605. clockEnergy=3.823849e+00
  606. maxBranches=22
  607. windowRdWrEnergy=3.958168e-01
  608. archBits  =32
  609. LSQBanks  =1
  610. [IntPred1_L]
  611. numPorts  =1
  612. WrHitEnergy=5.346558e-01
  613. WrMissEnergy=1.069312e+00
  614. Assoc     =32
  615. size      =256
  616. RdHitEnergy=5.346558e-01
  617. IDPnChildMax=4
  618. bSize     =8
  619. ReplPolicy='LRU'
  620. portOccp  =1
  621. RdMissEnergy=1.069312e+00
  622. deviceType='cache'
  623. [FXClusterIssueX_L]
  624. iMultUnit ='ALUIssueX_L'
  625. iMultLat  =8
  626. wakeUpPortOccp=1
  627. recycleAt ='Execute'
  628. wakeupDelay=3
  629. schedNumPorts=4
  630. iLoadLat  =1
  631. schedPortOccp=1
  632. iStoreLat =1
  633. iBJUnit   ='ALUIssueX_L'
  634. iLoadUnit ='LDIssueX_L'
  635. iDivLat   =23
  636. iDivUnit  ='ALUIssueX_L'
  637. iALUUnit  ='ALUIssueX_L'
  638. blockName ='IntWin'
  639. winSize   =68
  640. iALULat   =1
  641. schedDelay=1
  642. iBJLat    =1
  643. iStoreUnit='STIssueX_L'
  644. windowRdWrEnergy=6.876807e-01
  645. wakeUpNumPorts=4
  649. [FPClusterIssueX_L]
  650. winSize   =32
  651. recycleAt ='Execute'
  652. fpDivLat  =21
  653. schedPortOccp=1
  654. wakeUpNumPorts=4
  655. fpMultUnit='FP0IssueX_L'
  656. fpALULat  =3
  657. schedNumPorts=4
  658. blockName ='FPWin'
  659. fpALUUnit ='FP0IssueX_L'
  660. fpDivUnit ='FP0IssueX_L'
  661. windowRdWrEnergy=5.641608e-01
  662. fpMultLat =5
  663. schedDelay=1
  664. wakeUpPortOccp=1
  665. wakeupDelay=3
  666. [DataL1_L]
  667. bsize     =64
  668. replPolicy='RANDOM'
  669. portOccp  =1
  670. MSHR      ='DL1MSHR_L'
  671. numPorts  =1
  672. size      =32768
  673. RdMissEnergy=2.130306e+00
  674. WrHitEnergy=1.065153e+00
  675. assoc     =4
  676. hitDelay  =2
  677. missDelay =1
  678. WrMissEnergy=2.130306e+00
  679. lowerLevel="CommonBus Bus shared"
  680. blockName ='Dcache'
  681. RdHitEnergy=1.065153e+00
  682. deviceType='cache'
  683. skew      =false
  684. writePolicy='WB'
  685. [FXITLB_L]
  686. WrHitEnergy=6.515196e-01
  687. bsize     =8
  688. RdMissEnergy=1.303039e+00
  689. numPorts  =1
  690. deviceType='tlb'
  691. RdHitEnergy=6.515196e-01
  692. assoc     =32
  693. size      =256
  694. replPolicy='LRU'
  695. WrMissEnergy=1.303039e+00
  696. [BPredIssueX_L]
  697. l2Bits    =1
  698. btbReplPolicy='LRU'
  699. localBits =2
  700. BTACDelay =0
  701. l1size    =1
  702. localSize =16384
  703. btbSize   =2048
  704. rasSize   =0
  705. btbBsize  =1
  706. MetaBits  =2
  707. bpred4Cycle=1
  708. Metasize  =16384
  709. historySize=11
  710. l2size    =16384
  711. type      ='hybrid'
  712. btbAssoc  =2
  715. [DL1MSHR_L]
  716. size      =32
  717. type      ='full'
  718. bsize     =64
  721. [BigMemMSHR_L]
  722. type      ='none'
  723. size      =32
  724. bsize     =64
  725. [InstL1_L]
  726. blockName ='Icache'
  727. missDelay =0
  728. lowerLevel="L2Cache L2 shared"
  729. RdHitEnergy=1.135176e+00
  730. portOccp  =1
  731. MSHR      ='InstL1MSHR_L'
  732. hitDelay  =2
  733. assoc     =2
  734. RdMissEnergy=2.270351e+00
  735. deviceType='icache'
  736. size      =32768
  737. bsize     =64
  738. WrMissEnergy=2.270351e+00
  739. writePolicy='WB'
  740. WrHitEnergy=1.135176e+00
  741. replPolicy='LRU'
  742. numPorts  =2
  745. [BigMem_L]
  746. RdMissEnergy=0.000000e+00
  747. assoc     =1
  748. WrMissEnergy=0.000000e+00
  749. bsize     =64
  750. portOccp  =1
  751. RdHitEnergy=0.000000e+00
  752. hitDelay  =490
  753. numPorts  =1
  754. MSHR      ='BigMemMSHR_L'
  755. replPolicy='LRU'
  756. lowerLevel='voidDevice'
  757. missDelay =1600000
  758. WrHitEnergy=0.000000e+00
  759. deviceType='niceCache'
  760. size      =1024
  761. writePolicy='WB'
  764. [PBuffStream_L]
  765. BSize     =8
  766. RdMissEnergy=2.105553e+00
  767. numPorts  =2
  768. ReplPolicy='LRU'
  769. deviceType='cache'
  770. WrHitEnergy=1.052776e+00
  771. Assoc     =16
  772. WrMissEnergy=2.105553e+00
  773. RdHitEnergy=1.052776e+00
  774. portOccp  =3
  775. Size      =128
  782. [PBuffBuff_L]
  783. Assoc     =4
  784. WrMissEnergy=3.573363e+00
  785. WrHitEnergy=1.786681e+00
  786. RdMissEnergy=3.573363e+00
  787. ReplPolicy='LRU'
  788. deviceType='cache'
  789. BSize     =32
  790. portOccp  =3
  791. Size      =16384
  792. numPorts  =2
  793. RdHitEnergy=1.786681e+00
  796. [MSHRL2_L]
  797. bsize     =64
  798. type      ='full'
  799. size      =32
  800. [STIssueX_L]
  801. Occ = 1 
  802. Num = 3
  803. [LDIssueX_L]
  804. Occ       =1
  805. Num       =3
  806. [InstL1MSHR_L]
  807. size      =4
  808. type      ='full'
  809. bsize     =64
  810. [layer2]
  811. material  ='Virtual'
  812. thickness =0
  813. [ALUIssueX_L]
  814. Num = 8
  815. Occ = 1
  817. [FP0IssueX_L]
  818. Num       =1
  819. Occ       =1
  • 这里使用的基于SESC API的多进程程序如下：
  2. #include <unistd.h>
  3. #include <stdio.h>
  4. #include <stdlib.h>
  5. #include <string.h>
  6. #include"sescapi.h"
  7. struct thread_data
  8. {
  9.   int argc;
  10.   char **argv;
  11.   int done;
  12. };
  15. int basicmath_main(void *);
  16. int bitcount_main(void *);
  17. int cjpeg_main(void *);
  18. int djpeg_main(void *);
  19. int dijkstra_large_main(void *);
  20. int patricia_main(void *);
  21. int stringsearch_large_main(void *);
  22. int sha_main(void *);
  23. int rawdaudio_main(void *);
  24. int rawcaudio_main(void *);
  25. int CRC32_main(void *);
  26. int fft_main(void *);
  27. int fft_main(void *);
  28. #define numP 9
  29. int main(int argc, char *argv[]) {
  30. int i,j,k;
  31. struct thread_data ** thread_args = (struct thread_data**)malloc(numP * sizeof(struct thrad_data*));
  32. for(j = 0; j < numP; j++){
  33.     thread_args[j] = (struct thread_data *) malloc(sizeof(struct thread_data));
  34. }
  36.  i =  0 ;
  37. thread_args[i]->argc = 8;
  38. thread_args[i]->argv = (char **)malloc(8*sizeof(char *));
  39. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  40. memcpy(thread_args[i]->argv[0],"cjpeg_mian",20) ;
  41. thread_args[i]->argv[1] = (char *)malloc(20 *sizeof(char));
  42. memcpy(thread_args[i]->argv[1],"-dct",20); 
  43. thread_args[i]->argv[2] = (char *)malloc(20 *sizeof(char));
  44. memcpy(thread_args[i]->argv[2],"int",20); 
  45. thread_args[i]->argv[3] = (char *)malloc(20 *sizeof(char));
  46. memcpy(thread_args[i]->argv[3],"-progressive",20); 
  47. thread_args[i]->argv[4] = (char *)malloc(20 *sizeof(char));
  48. memcpy(thread_args[i]->argv[4],"-opt",20); 
  49. thread_args[i]->argv[5] = (char *)malloc(20 *sizeof(char));
  50. memcpy(thread_args[i]->argv[5],"-outfile",20); 
  51. thread_args[i]->argv[6] = (char *)malloc(30 *sizeof(char));
  52. memcpy(thread_args[i]->argv[6],"output_large_encode.jpeg",30); 
  53. thread_args[i]->argv[7] = (char *)malloc(20 *sizeof(char));
  54. memcpy(thread_args[i]->argv[7],"input_large.ppm",20); 
  57.  i =  1 ;
  58. thread_args[i]->argc = 2;
  59. thread_args[i]->argv = (char **)malloc(2*sizeof(char *));
  60. thread_args[i]->argv[0] = (char *)malloc(30 *sizeof(char));
  61. memcpy(thread_args[i]->argv[0],"dijkstra_large_mian",30); 
  62. thread_args[i]->argv[1] = (char *)malloc(20 *sizeof(char));
  63. memcpy(thread_args[i]->argv[1],"input.dat",20); 
  66.  i =  2 ;
  67. thread_args[i]->argc = 2;
  68. thread_args[i]->argv = (char **)malloc(2*sizeof(char *));
  69. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  70. memcpy(thread_args[i]->argv[0],"patricia_mian",20); 
  71. thread_args[i]->argv[1] = (char *)malloc(20 *sizeof(char));
  72. memcpy(thread_args[i]->argv[1],"large.udp",20); 
  75.  i =  3 ;
  76. thread_args[i]->argc = 1;
  77. thread_args[i]->argv = (char **)malloc(sizeof(char *));
  78. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  79. memcpy(thread_args[i]->argv[0],"search_large_mian",20); 
  82.  i =  4 ;
  83. thread_args[i]->argc = 2;
  84. thread_args[i]->argv = (char **)malloc(2*sizeof(char *));
  85. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  86. memcpy(thread_args[i]->argv[0],"sha_mian",20); 
  87. thread_args[i]->argv[1] = (char *)malloc(20 *sizeof(char));
  88. memcpy(thread_args[i]->argv[1],"input_large.asc",20); 
  91.  i =  5 ;
  92. thread_args[i]->argc = 1;
  93. thread_args[i]->argv = (char **)malloc(2*sizeof(char *));
  94. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  95. memcpy(thread_args[i]->argv[0],"rawcaudio_mian",20); 
  98.  i =  6 ;
  99. thread_args[i]->argc = 3;
  100. thread_args[i]->argv = (char **)malloc(3*sizeof(char *));
  101. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  102. memcpy(thread_args[i]->argv[0],"fft_mian",20); 
  103. thread_args[i]->argv[1] = (char *)malloc(20 *sizeof(char));
  104. memcpy(thread_args[i]->argv[1],"8",20); 
  105. thread_args[i]->argv[2] = (char *)malloc(20 *sizeof(char));
  106. memcpy(thread_args[i]->argv[2],"32768",20); 
  109.  i =  7 ;
  110. thread_args[i]->argc = 4;
  111. thread_args[i]->argv = (char **)malloc(4*sizeof(char *));
  112. thread_args[i]->argv[0] = (char *)malloc(20 *sizeof(char));
  113. memcpy(thread_args[i]->argv[0],"fft_mian",20); 
  114. thread_args[i]->argv[1] = (char *)malloc(20 *sizeof(char));
  115. memcpy(thread_args[i]->argv[1],"8",20); 
  116. thread_args[i]->argv[2] = (char *)malloc(20 *sizeof(char));
  117. memcpy(thread_args[i]->argv[2],"32768",20); 
  118. thread_args[i]->argv[3] = (char *)malloc(20 *sizeof(char));
  119. memcpy(thread_args[i]->argv[3],"-i",20); 
  122.  i =  0 ;
  123. sesc_spawn((void*)cjpeg_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  125.  i =  1 ;
  126. sesc_spawn((void*)dijkstra_large_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  128.  i =  2 ;
  129. sesc_spawn((void*)patricia_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  131.  i =  3 ;
  132. sesc_spawn((void*)stringsearch_large_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  134.  i =  4 ;
  135. sesc_spawn((void*)sha_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  137.  i =  5 ;
  138. sesc_spawn((void*)rawcaudio_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  140.  i =  6 ;
  141. sesc_spawn((void*)fft_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  143.  i =  7 ;
  144. sesc_spawn((void*)fft_main,(void *)thread_args[i],SESC_FLAG_MAP| i + 1);
  146. }
  • 上述程序运行结果如下：
  1. # Bench : ./sesc.mem -ccombina.conf -w100000 combina_1212 
  2. # File  : sesc_combina_1212.v6kaqg :       Sun Apr 17 10:27:59 2016
  3.       Exe Speed        Exe MHz         Exe Time         Sim Time (2400MHz)
  4.    1369.351 KIPS      0.7969 MHz     549.180 secs     182.350 msec (rabbit)
  5. Proc  Avg.Time BPType       Total          RAS           BPred          BTB            BTAC
  6.    1   156.985  hybrid       59.80% (100.00% of   9.04%)  55.80% ( 59.87% of  58.62%)   0.00% 
  7.    2   230.504  hybrid       99.18% (100.00% of   0.77%)  99.18% ( 98.60% of  36.16%)   0.00% 
  8.    3   236.339  hybrid       47.88% (100.00% of   8.02%)  43.33% ( 41.61% of  32.31%)   0.00% 
  9.    4   123.601  hybrid       92.16% (100.00% of   3.23%)  91.89% ( 88.71% of  42.08%)   0.00% 
  10.    5   209.454  hybrid       54.61% (100.00% of   7.59%)  50.88% ( 45.81% of  32.37%)   0.00% 
  11.    6   976.000  hybrid       25.00% (  0.00% of   0.00%)  25.00% (  0.00% of  12.50%)   0.00% 
  12.    7   35.086  hybrid       86.45% (100.00% of   8.55%)  85.18% ( 78.66% of  51.11%)   0.00% 
  13.    8   35.870  hybrid       87.05% (100.00% of   8.92%)  85.78% ( 79.32% of  47.09%)   0.00% 
  14.            nInst     BJ    Load   Store      INT      FP  : LD Forward , Replay : Worst Unit (clk)
  15.    1       11096  16.05%  18.56%  15.97%  49.41%   0.01%  :      0.24%   ????  inst/repl  :  LDIssueX_S 0.45 
  16.    2    67271313  10.80%  20.26%   4.67%  64.28%   0.00%  :      0.10%   ????  inst/repl  :  LDIssueX_S 0.02 
  17.    3        2063  20.55%  19.24%  15.08%  45.08%   0.05%  :      2.27%   ????  inst/repl  :  LDIssueX_S 0.39 
  18.    4     9735226  15.35%  22.02%  11.69%  50.93%   0.00%  :      0.68%   ????  inst/repl  :  LDIssueX_S 0.14 
  19.    5        2645  20.91%  20.79%  14.44%  43.82%   0.04%  :     13.82%    1322 inst/repl  :  STIssueX_L 0.04 
  20.    6          56  14.29%   5.36%  25.00%  53.57%   1.79%  :     66.67%   ????  inst/repl  :  STIssueX_L 0.04 
  21.    7   408228696  15.31%  24.60%  12.35%  41.18%   6.56%  :     33.62%      88 inst/repl  :  FP0IssueX_L 0.25 
  22.    8   266768970  14.17%  24.68%  11.59%  39.45%  10.11%  :     29.07%     150 inst/repl  :  FP0IssueX_L 0.25 
  23. Proc  IPC  Active       Cycles  Busy   LDQ   STQ  IWin   ROB  Regs Ports   TLB  maxBr MisBr Br4Clk  Other
  24.    1  0.08   0.03       133191   4.2   0.0   0.0  56.1   0.0   0.0   0.0   4.5   0.0   35.1    0.0    0.1 
  25.    2  0.16  93.22    407946995   8.2   0.0   0.0  91.4   0.0   0.0   0.0   0.0   0.0    0.3    0.0    0.0 
  26.    3  0.03   0.01        59650   1.7   0.0   0.0  29.3   0.0   0.0   0.0   8.0   0.0   60.9    0.0    0.0 
  27.    4  0.18  12.43     54394504   8.9   0.0   0.0  87.5   0.0   0.0   0.0   0.0   0.0    3.5    0.0    0.0 
  28.    5  0.05   0.01        58207   1.5   0.0   0.0   0.1   0.0   0.0   0.0   8.1   0.0   90.2    0.0    0.1 
  29.    6  0.01   0.00         6935   0.3   0.0   0.0   0.0   0.0   0.0   0.0  52.3   0.0   47.4    0.0    0.0 
  30.    7  0.93 100.00    437640780  31.1   2.9   0.0   1.9   6.5   0.3   0.0   0.2   0.0   54.3    0.1    2.6 
  31.    8  0.97  62.79    274810653  32.4   4.8   0.0   3.1   3.8   0.0   0.0   0.4   0.0   53.0    0.1    2.4 
  32. ################################################################################
  33. Proc CacheName LVID revLVID Energy : ... 
  34. ################################################################################
  35. Proc        Fetch     Issue      Mem       Exec     Clock     Total (watts)
  36. 0     0.001      0.000      0.087      0.000      1.582      1.670 
  37. 1     0.001      0.000      0.001      0.000      1.571      1.573 
  38. 2     0.086      0.393      0.273      0.524      1.725      3.000 
  39. 3     0.001      0.000      0.001      0.000      1.571      1.573 
  40. 4     0.014      0.057      0.051      0.094      1.597      1.813 
  41. 5     0.001      0.000      0.001      0.000      1.912      1.914 
  42. 6     0.001      0.000      0.001      0.000      1.912      1.914 
  43. 7     0.616      7.048      1.799      5.174      3.823     18.458 
  44. 8     0.390      4.609      1.186      3.377      3.160     12.722 
  45. Total     1.109     12.106      3.399      9.169     18.854     44.636

6.下周任务

  • 对SESC的使用进一步学习；
  • 对SESC进行AMP试验进一步了解；
  • 向师兄请教SESC支持AMP需要修改哪些文件，初步涉猎源码；
  • 师兄所给资料信息量巨大，需要经自己整理慢慢消化。
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